Flash Storage Devices

• Structure and functions of flash memory and controller.
• Typical issues. Controller configuration and its influence on user’s data.
• Chip-off solution for data retrieval.
• Standard and uncommon memory chip packages.
• TSOP and BGA packages.

NAND Flash Chips

• Raw NAND and managed NAND.
• Memory chip pin-outs and functions.
• Flash memory architecture and internal structure.
• Physical addressing.
• Crystals, Planes, Blocks, Pages and its sizes.
• Single and Multi-plane operations.
• Memory chip configuration.
• Chip ID, chip power, data bus.
• Async and DDR protocols.
• TLC-WL protocols.
• Memory chip reading modes.
• Reading physical image to file.
• Real-time chip access.
• Data transfer protocols.
• NAND chip defects.

Physical Image of Flash Memory Chips

• Addressing and structure of physical image.
• Banks, Blocks, Pages, Data area, Spare area.
• Page structure.
• Bad Columns.
• Data and Spare areas.
• Spare area structure.

Flash Controllers

• Controller types.
• Main functions.
• Read, Write, Erase operations.
• Virtual data transfer channel and data optimization.
• Data protection with ECC.
• Data transformations: Inversion, Scrambling (XOR).
• Virtual Block & Page allocation schemes.
• Flash Translation Layer (FTL).
• Block management.

Visual NAND Reconstrucor

• Software concept.
• Case concept. Database.
• Workspace.
• Virtual operations.
• Elements, parameters.
• Toolbar & Modes.
• Operatons with NAND chip.
• Automatic analysis modes.
• Dump Viewer and data vizualization modes.
• Hex viewer.
• Bitmap viewer

Pattern Analysis

• Bitmap usage for pattern analysis.
• Data patterns.
• Spare area paterns.
• Logical Block Number pattern.
• Logical Page Number pattern.
• Block Header pattern.
• ECC patterns.
• Scrambler (XOR patterns).
• Virtual block size detection.
• Page structure analysis.
• Data area detection.
• Spare area detection.

Physical Image Analysis and Data Recovery Practice

Hands-On practice sessions in the three phases of image analysis is a core component of this valuable training course and includes:

1. Physical Images
   • Bit error analysis in real-time chip access using Bitmap viewer.
   • Setting proper power levels for bit error minimization.
   • Physical image extraction.
   • Bad columns removal.
   • ECC detection.
2. Virtual Images
   • Physical image structure analysis and description using Bitmap viewer and Structure viewer (Virtual bock size, Page structure). Automatic Data area analysis.
   • Data transformations: Inversion and Scrambling (XOR) analysis using Bitmap viewer. Automatic Data transformation analysis.
   • Virtual block and page allocation analysis: multi-plane allocation, multi-chip serial and parallel allocation. Automatic Page allocation analysis.
3. Logical Images
   • Spare area analysis using Dump viewer modes. Automatic Spare area analysis. SA markers extraction and analysis: LBN, LPN, Header, ECC, Bank number, Write counter.
   • Setting up parameters of element “markers table” and translation table creation.
   • Translation table analysis: Block sorting and filtering. LBN chain integrity analysis: missing blocks and duplicated blocks.
   • Block arrange mode and list creation: Main blocks, Replacement blocks, LOG blocks.
   • Reconstruction of logical image.

Upon course completion, attendees will receive an official Certificate of Completion which includes the ruSolut stamp, ruSolut CEO’s signature and ruSolut Watemark. This certificate is the only recognized certificate that an attendee has successfully completed this valuable training.